Thermal management of multi-chip electronic packages is critical to ideal performance of both single and multi-chip electronic packages. Currently, management of thermal performance in multi-chip electronic packages is provided by encapsulating chips between a lid (e.g., heat spreader) and chip carrier using a thermal interface material (TIM) on the chips. For example, a TIM is dispensed on the chip and a lid is then pressed on the TIM to dissipate the heat generated by the chip, in the packaged assembly.
Adhesion of TIM between the lid and chip interface needs to be optimized in order to ensure adequate thermal performance. This is especially important due to increases in the chip size (e.g., higher than 20 mm) placed on an organic laminate. That is, due to the larger package, the stability and the adhesion of TIM undergo increased stresses due to thermal mismatch between the organic laminate and the chip. These stresses can result in delamination of TIM due to the bending of the package. Also, voiding phenomenon of the TIM decreases thermal performance of the package, which is also directly related to lack of coverage and reduced adhesion.